library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity somador_8bits is
	port(
		cin  : in std_logic;
      a, b : in std_logic_vector(7 downto 0);
      f    : out std_logic_vector(7 downto 0)
	);
end somador_8bits;

architecture arquitetura of somador_8bits is

	signal c: std_logic_vector(7 downto 0);

	component full_adder
		port (
			cin, a, b : in std_logic;
         f, cout : out std_logic
      );
	end component;

begin

   somabit0 : full_adder port map (cin, a(0), b(0), f(0), c(0));
   somabit1 : full_adder port map (c(0), a(1), b(1), f(1), c(1));
   somabit2 : full_adder port map (c(1), a(2), b(2), f(2), c(2));
   somabit3 : full_adder port map (c(2), a(3), b(3), f(3), c(3));
   somabit4 : full_adder port map (c(3), a(4), b(4), f(4), c(4));
   somabit5 : full_adder port map (c(4), a(5), b(5), f(5), c(5));
   somabit6 : full_adder port map (c(5), a(6), b(6), f(6), c(6));
   somabit7 : full_adder port map (c(6), a(7), b(7), f(7), c(7));

end arquitetura;
